000 00459nam a2200193Ia 4500
003 STCL
008 230726s9999 xx 000 0 und d
020 _a9788177589184
040 _aSTCL
_cSTCL
_bEN
082 _222
100 _aPalnitkar, Samir
245 0 _aVerilog HDL: a guide to digital design and synthesis
250 _a2
260 _bPearson
_aNoida
_c2022
300 _a490 p
365 _b699
546 _aEnglish
942 _2DDC
_e22
_cBKDDC
999 _c88992
_d88992